\begin{abstract}

Three-dimensional (3D) ICs promise to overcome barriers in integration density
and interconnect scaling by leveraging fast, dense inter-die vias, thereby
offering benefits of improved performance, higher memory bandwidth, smaller
form factors, and heterogeneous integration. 3D integration provides additional
architectural and technology-related design options for future system-on-chip (SoC) designs, making the early design space exploration more critical. This paper proposes
 a system-level design partition and hardware/software
co-synthesis framework for 3D SoC integration. The proposed methodology can be used to explore the enlarged design
space and find out the best design choices for given design constraints including form
factor, performance, power, or yield.
\end{abstract}

\vspace{5pt}
\section{Introduction}\label{sec:intro}

To further improve integration density and to tackle the interconnect challenge
as technology continues scaling, researchers have been pushing forward
three-dimensional (3D) IC stacking~\cite{Davis2005,Xie2006}. In a 3D IC,
multiple device layers are stacked together with direct vertical interconnects
through substrates. 3D ICs offer a number of advantages over traditional
two-dimensional (2D) designs, such as (1) higher packing density and smaller
footprint; (2) shorter global interconnect due to the short length of
through-silicon vias (TSVs) and the flexibility of vertical routing, leading to
higher performance and lower power consumption of interconnects; (3) support of
heterogenous integration: each single die can have different technologies.
Consequently, 3D IC designs have drawn a lot of attentions from both academia
and industry in recent years.

\begin{figure}
\centering
  % Requires \usepackage{graphicx}
  \includegraphics[width=0.33\textwidth]{./figures/challenge.pdf}\\
  \caption{Design space exploration in both technology and architecture options for 3D SoCs.}\label{fig:challenge}
\end{figure}

As we pack more and more transistors into a single chip, the pace of
productivity gains has not kept up to address the increases in design
complexity. Consequently, we have seen a recent trend of moving design
abstraction to a higher level, with an emphasis on \textbf{Electronic System
Level (ESL)} design methodologies. Electronic System Level is an established
approach built upon high-level abstracted languages such as C/C++, and is now
being used increasingly in System-on-Chip (SoC) design. From its genesis as an
algorithm modeling methodology with ``no links to implementation'', ESL is
evolving into a set of complementary methodologies that enable embedded system
design, verification, and debugging through to the hardware and software
implementation of custom SoC systems~\cite{Bailey2007}.

A common theme that runs through all of the current thinking in EDA and
system-level design these days is that complex design is best addressed at the
architectural level and very early in the design phase rather than later in the
design. Consequently, there has been intensive research on architectural design
space exploration for SoCs, with an emphasis on design partitioning and
hardware/software co-synthesis. In conventional system-level exploration,
designers consider trade-off in the way hardware and software components of a
system work together to exhibit a specified behavior, given a set of
performance goals and technology. In the scenario of 3D SoC integration, the
stacking strategies and 3D-related technology options will further complicate
the design space exploration, as shown in Fig.~\ref{fig:challenge}. It is
believed that if ESL is important for 2D designs, it will be critical for 3D
designs. A system-level design space exploration methodology that helps make the decisions at the
early stage of 3D SoC design is therefore of great importance.

This paper describes a methodology that explores the system-level design
space of 3D SoCs and finds out the design options leading to minimal
implementation cost under given design constraints. The paper is organized as follows. Section~\ref{sec:backgroud}
presents several preliminaries and introduces a generic cost metric to evaluate
the quality of design options with a motivational example. A system-level
synthesis framework incorporating task scheduling, resource allocation, layer
assignment and performance evaluation is then proposed in
Section~\ref{sec:framework} to achieve the goal. In Section~\ref{sec:analysis}
experiment analysis and case studies show that the proposed methodology is able
to produce the optimal design choices for the given 3D SoCs design instances.


\vspace{5pt}
\section{Preliminaries and Motivational Example}\label{sec:backgroud}

This section provides some preliminaries on 3D IC stacking and architectural
co-design, and presents a simple case discussion which motivates the work in
this paper.

\subsection{Preliminaries on 3D IC Stacking}

\begin{figure}
\centering
  % Requires \usepackage{graphicx}
  \includegraphics[width=0.4\textwidth]{./figures/3dexample.pdf}\\
  \caption{An illustration of 3D stacking technology.}\label{fig:3D}
\end{figure}

3D ICs can provide advanced system integration by stacking different dies into
a single chip.  The layers could be connected with wire bonding, TSV,
microbump, or even inductive/capacitive contact~\cite{Davis2005}. TSV-based 3D
technology, as shown in Fig.~\ref{fig:3D}, provides the possibility for high
density interconnection between the layers by the mean creating vertical
connections through the silicon substrate, and consequently is the focus of the
majority of current research on 3D integration technologies.
\textit{Die-to-wafer (D2W)} and \textit{wafer-to-wafer (W2W)} are two different
ways to bond multiple dies in TSV-based 3D integration. W2W bonding stacks all
layers of wafer before a single 3D chip is sliced and packaged, while D2W
bonding mount different layer of dies onto the base wafer sequentially.

\subsection{Preliminaries on Architectural Co-design}

\begin{figure}
\centering
  % Requires \usepackage{graphicx}
  \includegraphics[width=0.28\textwidth, angle=-90]{./figures/ESL.pdf}\\
  \caption{Conventional ESL Design Flow for 2D Chips.}\label{fig:ESL}
\end{figure}

Nowadays SoCs are implemented as mixed software-hardware systems. The software
components usually run on general processor cores, while hardware components
consist of accelerators, custom IPs, etc. Generally, software is used for
features and flexibility, while hardware is used for performance. While a given
functionality could be implemented on either hardware or software, the two
choices might have different impacts on performance, power or other metrics,
leading to different costs. Therefore, an unified architectural
hardware/software co-synthesis methodology is required to minimize cost of
implementation while satisfying all the design constraints. Fig.~\ref{fig:ESL}
shows a typical architectural synthesis flow for 2D chips. The flow takes as
input a task graph and a component library including both hardware and software
models, determines the assignments of tasks to different components, and
evaluates the performance iteratively to find out the best design options.


\subsection{An Motivational Example}

\begin{figure}
\centering
  % Requires \usepackage{graphicx}
  \includegraphics[width=0.28\textwidth]{./figures/example.pdf}\\
  \caption{An Motivational Example on Design Choice Exploration for 3D SoCs.}\label{fig:example}
\end{figure}

For conventional 2D SoC design, the logic circuits and on-chip memory are put
onto one single layer. The flexibility during early design stage is limited.
After the introduction of 3D ICs, design space is enlarged by additional design
choices. The number of layers, the stacking strategies, the interconnect
bandwidth provided by 3D stacking technology are all flexible to decide during
early stage of design phase. Fig.~\ref{fig:example} shows one motivational
example. This simplified SoC design uses a 2 layer logic-to-memory stacking,
with a micro-processor in the lower layer and DRAM
 memory in the upper layer. Designers can choose to either use high frequency
memory (528MHz DDR with 32-bit interface) with a small number of TSVs, or low
frequency memory (66MHz SDR with 4$\times$128-bit parallel interface) with a
larger number of TSVs. Even with 8 times lower frequency, the second
implementation can still provide the same bandwidth as the first one (Note that
DDR memory has doubled data rate). The tradeoff between these two
implementations is the number of TSVs (100 v.s 1000) with corresponding chip
area overhead, and the chip power consumption. These can be translated to
different implementation cost. In this paper, we present optimized design
choices based on various preferences of designers, using the proposed 3D
integration synthesis framework.
